555 astable timer
Analyse or size classic and diode-steered 555 timing networks.
Development preview. Check the assumptions below before relying on a result. Calculations run in your browser.
How it calculates
Model: Standard: tH=ln(2)(R1+R2)C, tL=ln(2)R2C. Steering: tH=R1C ln[(2VCC/3−Vf)/(VCC/3−Vf)].
Assumptions
- Thresholds idealised at 1/3 and 2/3 supply; discharge saturation, leakage and propagation delay are omitted.
- NE555 is bipolar; TLC555/LMC555 are CMOS with lower input and supply currents. Enter the selected part’s actual quiescent current; the input is not automatically changed by family selection.
- Supply estimate excludes output load and switching spikes; R1 also conducts during the discharge interval.
Worked example
These are the calculator's default inputs. Change any input above to recalculate.
Inputs
- Mode
- analyse
- Timing path
- standard
- Device family
- NE555
- Charge resistor R1
- 10000 Ω
- Discharge resistor R2
- 10000 Ω
- Timing capacitance
- 0.000001 F
- Design frequency
- 100 Hz
- Design output-high duty
- 60 %
- Supply voltage
- 5 V
- Steering diode forward drop
- 0.3 V
- Entered IC quiescent supply current
- 0.003 A
Results
- Frequency
- 48.0898 Hz
- High duty
- 66.6667 %
- R1
- 10000 Ω
- R2
- 10000 Ω
- High interval
- 0.0138629 s
- Low interval
- 0.00693147 s
- Estimated no-load supply current
- 0.00324682 A