SDG Electronics

ADC anti alias filter

ADC anti alias filter with computed response and explicit circuit realisation.

Development preview. Check the assumptions below before relying on a result. Calculations run in your browser.

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How it calculates

Alias stop edge: fstop = fs − fpass

Half-LSB rejection: Astop = 20 log10(Ainterferer × 2^(N+1))

Butterworth order: n ≥ log10[(10^(As/10)−1)/(10^(Ap/10)−1)]/[2 log10(fs/fp)]

Chebyshev order: n ≥ acosh(√[(10^(As/10)−1)/(10^(Ap/10)−1)])/acosh(fs/fp)

Assumptions

  • The interferer amplitude is relative to ADC full scale. Passband droop and nearest-image attenuation define the minimum ideal order. Bessel order is searched from computed −3 dB prototypes. Actual component/driver/ADC responses must be included before hardware sign-off.

Worked example

These are the calculator's default inputs. Change any input above to recalculate.

Inputs

Sampling frequency
48000 Hz
Passband edge
10000 Hz
ADC target bits
12 bits
Out-of-band input / full-scale amplitude
1
Allowed passband attenuation
0.5 dB
Prototype
butterworth

Results

Minimum order
8
Required corner or ripple-edge frequency
11405.1 Hz
First alias stopband edge
38000 Hz
Required rejection
78.2678 dB
Rejection at alias edge
83.6296 dB

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