SDG Electronics

ADC charge bucket RC

ADC charge bucket RC with explicit circuit assumptions and worked equations.

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How it calculates

Full-step recovery: error = VFS exp[−tacq/((Rs + Rf)(Cf + Csh))]

Charge sharing: ΔVinitial = VFS Csh/(Cf + Csh)

Half-LSB time: tsettle = (Rs + Rf)(Cf + Csh)(N + 1) ln 2

Assumptions

  • First-order lumped RC model. The charge-sharing case assumes Cf starts at the correct signal voltage and Csh starts one full-scale away. Full-step result assumes both capacitors see a new full-scale input. Switch resistance, amplifier dynamics, kickback spectrum and dielectric absorption are omitted; use OA-20 for an amplifier approximation.

Worked example

These are the calculator's default inputs. Change any input above to recalculate.

Inputs

Filter resistance
100 Ω
Source resistance
10 Ω
Filter capacitor
2e-9 F
Sample capacitor
2e-11 F
ADC resolution
12 bits
Acquisition time
0.000001 s
Full-scale step
3.3 V

Results

Charge sharing residual
0.450317 LSB
Full-scale step residual
45.482 LSB
Filter/sample capacitance ratio
100
RC corner
716269 Hz
Maximum total R for full-scale acquisition
54.9389 Ω
Full-scale settling time
0.00000200222 s

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