SDG Electronics

BJT current mirrors

Matched simple, Wilson and Widlar mirror estimates including base-current error.

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How it calculates

Widlar solution: ln(IC1/IO) = IO(1+1/β)RE/VT; IREF = IC1(1+1/β)+IO/β

Assumptions

  • Matched transistor temperature, beta and saturation current. Nominal current excludes Early-effect mismatch.
  • Feedback sink: Q1 emitter feeds RE to ground; Q2 senses the RE voltage and pulls down Q1 base. IREF feeds their shared base/collector node. IOUT approaches VBE(Q2)/RE; finite equal beta is included. Output resistance is not inferred without a full feedback model.
  • Wilson current ratio and output resistance are first-order matched-device approximations; minimum compliance uses VBE + 0.2 V.

Worked example

These are the calculator's default inputs. Change any input above to recalculate.

Inputs

Mirror
simple
Reference current
0.001 A
Matched beta
100
Widlar / feedback-sink emitter resistor
1000 Ω
Early voltage
100 V
Reference VBE
0.7 V
Available output voltage
5 V
Device temperature
25 °C

Results

Output current
0.000980392 A
Current error
-1.96078 %
Approximate minimum output voltage
0.2 V
Approximate output resistance
102000 Ω
Output-transistor dissipation
0.00490196 W

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