SDG Electronics

Clock baud and ppm error

Integer-divider frequency/baud selection, signed error, oscillator budget and accumulated drift.

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How it calculates

Model: factual=fclock/(prescaler×integer divider); ppm=10⁶(factual/ftarget−1); drift=elapsed×frequency error.

Assumptions

  • Generic integer-divider equation: a controller register may hold divider−1 or use fractional divisors, which are not inferred.
  • Clock budget adds absolute initial, temperature and ageing bounds. Time error describes nominal-clock-indicated time minus reference elapsed time.

Worked example

These are the calculator's default inputs. Change any input above to recalculate.

Inputs

Divider mode
choose nearest
Input clock
16000000 Hz
Target frequency or baud
115200 Hz
Prescaler / oversampling factor
16
Entered integer divider
9
Initial oscillator tolerance
20 ppm
Temperature tolerance
30 ppm
Ageing allowance
5 ppm
Elapsed time
86400 s

Results

Integer divider
9
Actual nominal frequency
111111 Hz
Signed nominal error
-3.54938 %
Signed nominal error
-35493.8 ppm
Worst lower frequency
111105 Hz
Worst upper frequency
111117 Hz
Nominal accumulated time error
-3066.67 s
Worst absolute time error
3071.25 s

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