SDG Electronics

Logic gates and truth tables

Standard logic gates and a bounded Boolean-expression parser with no code evaluation.

Development preview. Check the assumptions below before relying on a result. Calculations run in your browser.

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How it calculates

Model: Precedence: parentheses, NOT, AND/NAND, XOR/XNOR, OR/NOR. Binary operators of the same precedence associate left to right.

Assumptions

  • At most eight variables (A–H), 256 rows, 160 tokens and 24 nesting levels. No timing, analogue thresholds or general circuit simulation.

Worked example

These are the calculator's default inputs. Change any input above to recalculate.

Inputs

Gate or expression
AND
Expression
(A AND B) OR NOT C

Results

Evaluated expression
A AND B
Variables
A, B
Truth-table rows
4
Rows with output 1
1
Rows with output 0
3

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