Output capacitor and load transients
Ripple, ESR/ESL steps, loop-delay charge deficit and energy-conservation overshoot bounds.
Development preview. Check the assumptions below before relying on a result. Calculations run in your browser.
How it calculates
Assumptions
- Charge deficit approximates a delayed first-order current response with time constant 1/(2πfc); crossover alone does not determine a real converter transient.
- Energy overshoot assumes all released inductor energy reaches the capacitor, with no simultaneous load or loss; it is a conservative energy bound.
- Identical capacitors share current equally. ESL spike uses the user-entered load-edge time and excludes interconnect inductance.
Worked example
These are the calculator's default inputs. Change any input above to recalculate.
Inputs
- Output voltage
- 5 V
- Each nominal capacitor
- 0.0001 F
- Parallel capacitor count
- 2
- Capacitance retention
- 0.7
- Each capacitor ESR
- 0.03 Ω
- Each capacitor ESL
- 1e-9 H
- Triangular ripple current peak-to-peak
- 0.4 A
- Ripple frequency
- 300000 Hz
- Load-current step magnitude
- 1 A
- Load-step transition time
- 0.000001 s
- Assumed loop crossover
- 10000 Hz
- Additional control delay
- 0.000001 s
- Output inductance
- 0.000022 H
- Inductor current before load release
- 2 A
- Final current after release
- 1 A
- Allowed output deviation
- 0.2 V
Results
- Capacitance for chosen transient budget
- 0.0000916829 F
- Additive undershoot estimate
- 0.136325 V
- Effective parallel capacitance
- 0.00014 F
- Triangular capacitive + ESR ripple
- 0.00719048 V
- ESR load step
- 0.015 V
- ESL edge spike
- 0.0005 V
- Loop-delay charge-deficit droop
- 0.120825 V
- Stored-inductor-energy overshoot bound
- 0.0469227 V