PWM DAC ripple and settling
Exact periodic RC response or two buffered equal-RC poles, with ripple and N-bit settling.
Development preview. Check the assumptions below before relying on a result. Calculations run in your browser.
How it calculates
Model: One pole: exponential charge/discharge periodic equilibrium. Two equal buffered poles: y=U+[y0−U+(x0−U)t/RC]e^(−t/RC).
Assumptions
- Two-pole option requires an ideal buffer between identical RC stages; an unbuffered ladder has a different response.
- Ripple extrema are solved within each PWM segment. Settling is a full-scale step of the average command, separate from continuing PWM ripple.
Worked example
These are the calculator's default inputs. Change any input above to recalculate.
Inputs
- Filter
- one RC
- Each stage resistance
- 10000 Ω
- Each stage capacitance
- 1e-7 F
- PWM frequency
- 10000 Hz
- PWM high voltage
- 3.3 V
- Duty cycle
- 50 %
- Target resolution bits
- 10
Results
- Peak-to-peak ripple
- 0.0824828 V
- Full-step settling to ½ LSB
- 0.00762462 s
- Mean output
- 1.65 V
- Target LSB
- 0.00322266 V
- Ripple in LSB
- 25.5947
- Each-stage pole frequency
- 159.155 Hz