SDG Electronics

Regulator feedback divider

Regulator feedback divider with explicit circuit assumptions and worked equations.

Development preview. Check the assumptions below before relying on a result. Calculations run in your browser.

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How it calculates

Output: Vout = Vref(1 + Rt/Rb) + IFB Rt

Top resistor: Rt = (Vtarget − Vref)/(Vref/Rb + IFB)

Assumptions

  • Positive IFB flows from the divider node into the regulator FB pin. Reference and resistor tolerances are independent worst-case corners. Cff zero is the divider zero only; regulator loop stability is not inferred.

Worked example

These are the calculator's default inputs. Change any input above to recalculate.

Inputs

Solve
analyse
Feedback reference
1.25 V
Target output
5 V
Top resistor
30000 Ω
Bottom resistor
10000 Ω
FB current flowing into pin
0 A
Resistor tolerance
1 %
Reference tolerance
1 %
Feed-forward capacitor
0 F

Results

Output voltage
5 V
Top resistor
30000 Ω
Minimum output
4.87649 V
Maximum output
5.12652 V
Bottom-divider current
0.000125 A
Top resistor power
0.00046875 W
Feed-forward zero
No feed-forward capacitor Hz

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