SAR ADC amplifier driver
SAR ADC amplifier driver with circuit equations and operating-limit checks.
Development preview. Check the assumptions below before relying on a result. Calculations run in your browser.
How it calculates
Conservative settle budget: t = ΔV/SR + (τRC + τamp)(N+2) ln 2
Time constants: τRC = (Rsource+Riso)(Cf+Csh); τamp = NG/(2πGBW)
Residual bound: error/FS ≤ exp(−tavailable/(2τRC)) + exp(−tavailable/(2τamp))
Assumptions
- Budget allocates a quarter LSB to each linear first-order stage after a full slew interval; this is conservative and is not an exact nonlinear transient. Stability model is the OA-18 local-feedback approximation. Switch resistance, multiplexed charge transfer, ADC kickback details and amplifier overload recovery need device models. A low phase margin invalidates the first-order settling approximation.
Worked example
These are the calculator's default inputs. Change any input above to recalculate.
Inputs
- Amplifier GBW
- 1000000 Hz
- DC open-loop gain
- 100 dB
- Additional open-loop pole
- 10000000 Hz
- Open-loop output resistance
- 50 Ω
- Isolation resistor
- 47 Ω
- Load capacitance
- 1e-9 F
- Closed-loop noise gain
- 1
- DC load current
- 0.001 A
- ADC sample capacitor
- 2e-11 F
- Additional source resistance
- 10 Ω
- ADC bits
- 16 bits
- Acquisition time
- 0.000002 s
- Full-scale step
- 3.3 V
- Driver slew rate
- 1000000 V/s
Results
- Conservative combined settling
- 0.00000601111 s
- Conservative residual bound
- 65536 LSB
- Approximate loop phase margin
- 70.7913 deg
- RC half-LSB settling
- 7.25392e-7 s
- Amplifier linear half-LSB settling
- 0.00000198572 s