SDG #158 Assembling and testing the 10 MHz GPSDO Reference Prototype Board

This episode follows the first physical build of a 10 MHz GPSDO (GPS Disciplined Oscillator) reference prototype PCB, taking the design from bare fabricated board to a powered-up, locking unit on the bench. It is a useful watch for anyone who has designed a mixed signal board on paper and wants to see the reality of populating it: paste application, reflow on a cheap 946C style hotplate, hot air touch-up for the fine pitch parts, and the inevitable inspection pass under the microscope before any power goes near it.

The assembly commentary is more valuable than a straight build log because it highlights where a GPSDO design is unforgiving. Timing references live or die on the analogue side, so decoupling placement, ground return paths and the loop filter components around the OCXO or VCXO matter more than in a typical digital board. The video also shows why prototype boards should be brought up in stages: confirm rails first, then the GPS module’s serial output and 1PPS, and only then look at whether the control loop is actually pulling the oscillator into lock.

On the testing side, the focus is on proving basic functionality rather than chasing Allan deviation figures: verifying the GPS receiver acquires satellites, watching the lock indication settle, and checking the 10 MHz output waveform amplitude and shape at the connector. That distinction is worth noting if you are considering building your own reference; a board that outputs 10 MHz and claims lock is only the starting point, and real characterisation needs a second known-good reference for comparison. As a prototype milestone, it shows the design concept is sound while leaving clear items on the revision list.