SDG #159 Getting 10.000000000 MHz from the GPSDO using an FPGA and MCU

A GPS disciplined oscillator locks its OCXO to GPS time, but that does not automatically mean the front panel output is sitting at exactly 10 MHz. Because the control loop is steering the oscillator to minimise phase error against the 1PPS signal, the actual instantaneous frequency wanders slightly either side of nominal, and the DAC or EFC resolution limits how finely you can nudge it. That leaves a small but measurable offset that matters if you are using the GPSDO as a frequency reference rather than purely as a timing source.

This project tackles the problem the same way commercial instruments such as the SRS FS740 do: instead of relying on the oscillator alone, the raw OCXO output is fed into an FPGA that performs fractional division and synthesis, so the output frequency can be corrected in tiny increments under software control. An MCU handles the housekeeping, monitoring the phase measurement from the time interval counter and adjusting the FPGA’s division parameters to keep the synthesised output pinned to the correct value over long averaging periods.

The practical takeaway for anyone building a Lars-style Arduino GPSDO is that the hardware you already have can be pushed considerably further with a digital synthesis stage bolted on. The trade-offs are worth understanding: fractional division introduces jitter and spurs that a clean analogue OCXO output does not have, so there is a real tension between absolute frequency accuracy and short term phase noise. Which one you optimise for depends entirely on whether you are calibrating counters or feeding a low phase noise RF chain.